Chromite H SoC Manual Logo
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  • 1. Introduction
  • 2. Memory Map
  • 3. Getting Started
  • 4. Supported FPGAs
  • 5. OS Ports
  • 6. Core Pipeline
  • 7. Modes of Operation
  • 8. Custom CSRs
  • 9. Physical Memory Protection (PMP)
  • 10. Performance Monitors
  • 11. L1 Cache Subsytem
  • 12. Memory Management Unit (MMU)
  • 13. Interrupts
  • 14. Debug
  • 15. Debug Interface
  • 16. Boot Config
  • 17. General Purpose Input Output Controller
  • 18. Core Local Interrupt (CLINT)
  • 19. Platform Level Interrupt Controller (PLIC)
  • 20. Universal Asynchronous Receiver/Transmitter (UART)
  • 21. Pulse Width Modulation (PWM) Module
  • 22. Serial Peripheral Interface (SPI) Module
  • 23. QUAD Serial Peripheral Interface (QSPI) Module
  • 24. Licensing and Support
Chromite H SoC Manual
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